Configurable FPGA-Based Watchdog Timer for Real-Time Fault Detection in SCADA Energy Systems
DOI:
https://doi.org/10.63746/njtd.v23i2.4824Keywords:
FPGA, watchdog timer, SCADA, Fault detection, real-time systems, ReliabilityAbstract
Supervisory Control and Data Acquisition (SCADA) systems play a critical role in modern energy infrastructures, where reliable real-time fault detection is essential for maintaining operational safety and system availability. However, software execution faults, timing violations, and communication disturbances can compromise the effectiveness of conventional monitoring mechanisms. This work presents a configurable Field-Programmable Gate Array (FPGA)-based dual-window watchdog timer for real-time fault detection in SCADA-based energy systems. The objective is to provide deterministic hardware-level supervision capable of detecting abnormal software execution patterns and initiating appropriate recovery actions. The proposed dual-window watchdog architecture employs configurable service and frame windows implemented in Verilog Hardware Description Language (HDL) and integrates dedicated fault detection, fault classification, and reset-control logic. The watchdog detects missed-service, out-of-window service, and double-service faults while providing a dual-stage response mechanism consisting of fault signaling followed by delayed system reset. The design was implemented on a Xilinx Artix-7 FPGA and validated through simulation, synthesis, timing analysis, and experimental hardware measurements. Results demonstrated correct detection and classification of all considered fault conditions. Out-of-window service and double-service faults were detected within a single System Clock (SYSCLK) cycle after occurrence, whereas missed-service faults were detected upon frame-window expiration. Timing analysis confirmed stable operation up to 149.992 MHz with a critical-path delay of 5.421 ns and positive timing slack. Resource utilization remained below 1% of the available FPGA resources, with no inferred BRAM or DSP blocks. These results demonstrate the suitability of the proposed dual-window watchdog timer as an efficient, lightweight, and deterministic hardware supervision mechanism for SCADA-based energy systems.
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